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Subject[PATCH v1 11/50] clk: samsung: add IDs to UART clocks in Exynos5420
Date
Add IDs to MUXes for UART to manage them from DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c13f34d3d9a1..7bf74401c4e7 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -768,10 +768,10 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),

/* PERIC Block */
- MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
- MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
- MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
- MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+ MUX(CLK_MOUT_UART0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+ MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+ MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+ MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
--
2.17.1
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