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Subject[PATCH v1 34/50] ARM: dts: exynos: set parent clocks to PWM in Exynos5420
Date
Change the parent of PWM clock to the CPLL which has 666MHz.
The PWM's divider uses /10 rate so it would set 66.6MHz.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 79f635043247..a361dd5a6036 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1473,6 +1473,8 @@

&pwm {
clocks = <&clock CLK_PWM>;
+ assigned-clocks = <&clock CLK_MOUT_PWM>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
clock-names = "timers";
};

--
2.17.1
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