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SubjectRe: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
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Quoting chandanu@codeaurora.org (2019-02-01 16:05:55)
> On 2018-10-29 11:43, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-10-28 03:34:55)
> >> On 2018-10-19 16:04, Taniya Das wrote:
>
> >> >>
> >> >>> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
> >> >>> + .halt_reg = 0x2044,
> >> >>> + .halt_check = BRANCH_HALT,
> >> >>> + .clkr = {
> >> >>> + .enable_reg = 0x2044,
> >> >>> + .enable_mask = BIT(0),
> >> >>> + .hw.init = &(struct clk_init_data){
> >> >>> + .name = "disp_cc_mdss_dp_link_intf_clk",
> >> >>> + .parent_names = (const char *[]){
> >> >>> + "disp_cc_mdss_dp_link_clk_src",
> >> >>> + },
> >> >>> + .num_parents = 1,
> >> >>> + .flags = CLK_GET_RATE_NOCACHE,
> >> >>
> >> >> Why?
> >> >>
> >> >
> >> > It was a requirement, but let me get back on this too.
> >> >
> >> I had a discussion with the Display Port teams and below is the
> >> requirement,
> >>
> >> This flag is required since we reset/power-down the PLL every time
> >> they
> >> disconnect/connect the DP cable or during suspend/resume.
> >> Only with this flag, the calls to the PLL driver properly.
> >
> > Ok. So that explains the get rate nocache flag. Can you please add a
> > comment that explains that these clk registers here are lost across
> > suspend/resume of the display device? It really sounds like these
> > display clks are inside of the display power domain and thus they lose
> > their state across the display power domain power down. It would be
> > better if we could properly implement suspend/restore for these clk
> > registers across suspend/resume of the display device so that we don't
> > need this nocache flag and the display code can work together with the
> > clk code here to restore the frequency to the clk.
>

This patch came again and it didn't have any comments to this effect in
the code around the flag.

>
> We already handle the suspend/restore for these clk registers
> in Dp PLL domain. Without the "NOCACHE_FLAG", and if we are requesting
> the same clock rate
> for any of the clocks, the set_rate call never reaches the DP PLL Ops.

So do you restore the frequency of the PLL manually? Or that is done by
calling clk_set_rate() on the leaf clk again?

>
> I am not clear on what you are suggesting for removing the
> "NOCACHE_FLAG" for
> the DisplayPort clocks. Are you suggesting design changes in DP PLL
> driver or in dispcc-driver?
> Can you please provide more details?
>

I'm suggesting that the clk framework needs to be told that the PLL has
lost the rate and thus should do a save/restore of the registers so that
the clk framework can be back in sync with the clk hardware. Maybe it's
as simple as calling clk_set_rate(&pll, XO_RATE) or clk_set_parent(&pll,
&xo_clk), so that we can recalc the rate down the tree and fix up the
child clk frequencies. Or, maybe we need to add some sort of mechanism
to the clk framework so it can be told that the frequency here has
changed. Or we need to add a hook in the power domain for the DP PLL to
tell the clk framework that the clk has changed rate and thus should
recalc down to the children. Something like this, instead of an obtuse
flag that tells us very little about what's going on.

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