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SubjectRE: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors
Date
Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]
> Sent: 2019年6月12日 21:54
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; catalin.marinas@arm.com; will.deacon@arm.com;
> Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register
> accessors
>
> On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > There are some 8-bit and 16-bit registers in PCIe configuration space,
> > so add accessors for them.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> > ---
> > V5:
> > - Corrected and retouched the subject and changelog.
> > - No functionality change.
> >
> > drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 411e9779da12..456adfee393c 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie,
> u32 off)
> > return csr_read(pcie, off, 0x4);
> > }
> >
> > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) {
> > + return csr_read(pcie, off, 0x2);
> > +}
> > +
> > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) {
> > + return csr_read(pcie, off, 0x1);
> > +}
> > +
> > static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > {
> > csr_write(pcie, val, off, 0x4);
> > }
> >
> > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > +{
> > + csr_write(pcie, val, off, 0x2);
> > +}
> > +
> > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> > +{
> > + csr_write(pcie, val, off, 0x1);
> > +}
> > +
>
> They are not used so you should drop this patch.

NXP Layerscape PCIe Gen4 controller driver will use them, so don't drop it.

Thanks,
Zhiqiang

>
> Lorenzo
>
> > static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) {
> > return (csr_readl(pcie, LTSSM_STATUS) &
> > --
> > 2.17.1
> >
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