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SubjectRe: [PATCH 1/2] PCI: altera: Fix configuration type based on secondary number
On Thu, May 30, 2019 at 11:25 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Fri, May 24, 2019 at 02:07:25PM +0800, Ley Foon Tan wrote:
> > This fix issue when access config from PCIe switch.
> >
> > Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
> > as previous version (V1) does.
> >
> > The PCIe controller need to send Type 0 config TLP if the targeting bus
> > matches with the secondary bus number, which is when the TLP is targeting
> > the immediate device on the link.
> >
> > The PCIe controller send Type 1 config TLP if the targeting bus is
> > larger than the secondary bus, which is when the TLP is targeting the
> > device not immediate on the link.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> > ---
> > drivers/pci/controller/pcie-altera.c | 22 ++++++++++++++++++++--
> > 1 file changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> > index 27222071ace7..047bcc214f9b 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -44,6 +44,8 @@
> > #define S10_RP_RXCPL_STATUS 0x200C
> > #define S10_RP_CFG_ADDR(pcie, reg) \
> > (((pcie)->hip_base) + (reg) + (1 << 20))
> > +#define S10_RP_SECONDARY(pcie) \
> > + readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
> >
> > /* TLP configuration type 0 and 1 */
> > #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
> > @@ -63,6 +65,14 @@
> > ((((bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
> > : pcie->pcie_data->cfgwr1) << 24) | \
> > TLP_PAYLOAD_SIZE)
> > +#define S10_TLP_CFGRD_DW0(pcie, bus) \
> > + (((((bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgrd0 \
> > + : pcie->pcie_data->cfgrd1) << 24) | \
> > + TLP_PAYLOAD_SIZE)
> > +#define S10_TLP_CFGWR_DW0(pcie, bus) \
> > + (((((bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgwr0 \
> > + : pcie->pcie_data->cfgwr1) << 24) | \
> > + TLP_PAYLOAD_SIZE)
> > #define TLP_CFG_DW1(pcie, tag, be) \
> > (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
> > #define TLP_CFG_DW2(bus, devfn, offset) \
> > @@ -327,7 +337,11 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
> > {
> > u32 headers[TLP_HDR_SIZE];
> >
> > - headers[0] = TLP_CFGRD_DW0(pcie, bus);
> > + if (pcie->pcie_data->version == ALTERA_PCIE_V1)
> > + headers[0] = TLP_CFGRD_DW0(pcie, bus);
> > + else
> > + headers[0] = S10_TLP_CFGRD_DW0(pcie, bus);
> > +
> > headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
> > headers[2] = TLP_CFG_DW2(bus, devfn, where);
> >
> > @@ -342,7 +356,11 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
> > u32 headers[TLP_HDR_SIZE];
> > int ret;
> >
> > - headers[0] = TLP_CFGWR_DW0(pcie, bus);
> > + if (pcie->pcie_data->version == ALTERA_PCIE_V1)
> > + headers[0] = TLP_CFGWR_DW0(pcie, bus);
> > + else
> > + headers[0] = S10_TLP_CFGWR_DW0(pcie, bus);
> > +
>
> Why don't you rewrite all these macros as an eg:
>
> static inline u32 get_tlp_header()
> {}
>
> where you can also handle the version and everything needed to
> detect what header should be set-up ?
>
Okay, will change this.

Thanks.

Regards
Ley Foon

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