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SubjectRe: [PATCH 3/9] perf/x86/intel: Support overflows on SLOTS
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On 5/28/2019 8:20 AM, Peter Zijlstra wrote:
> On Tue, May 21, 2019 at 02:40:49PM -0700, kan.liang@linux.intel.com wrote:
>> From: Andi Kleen <ak@linux.intel.com>
>>
>> The internal counters used for the metrics can overflow. If this happens
>> an overflow is triggered on the SLOTS fixed counter. Add special code
>> that resets all the slave metric counters in this case.
>
> The SDM also talked about a OVF_PERF_METRICS overflow bit. Which seems
> to suggest something else.

Yes, I think we should handle the bit as well and only update metrics event.

It looks like bit 48 is occupied by INTEL_PMC_IDX_FIXED_BTS.
I will also change
INTEL_PMC_IDX_FIXED_BTS to INTEL_PMC_IDX_FIXED + 15.
INTEL_PMC_IDX_FIXED_METRIC_BASE to INTEL_PMC_IDX_FIXED + 16

Thanks,
Kan

>
>> Signed-off-by: Andi Kleen <ak@linux.intel.com>
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> ---
>> arch/x86/events/intel/core.c | 23 +++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 75ed91a36413..a66dc761f09d 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -2279,12 +2279,35 @@ static void intel_pmu_add_event(struct perf_event *event)
>> intel_pmu_lbr_add(event);
>> }
>>
>> +/* When SLOTS overflowed update all the active topdown-* events */
>> +static void intel_pmu_update_metrics(struct perf_event *event)
>> +{
>> + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>> + int idx;
>> + u64 slots_events;
>> +
>> + slots_events = *(u64 *)cpuc->enabled_events & INTEL_PMC_MSK_ANY_SLOTS;
>> +
>> + for_each_set_bit(idx, (unsigned long *)&slots_events, 64) {
>
> for (idx = INTEL_PMC_IDX_TD_RETIRING;
> idx <= INTEL_PMC_IDX_TD_BE_BOUND; idx++)
>
> perhaps?
>
>> + struct perf_event *ev = cpuc->events[idx];
>> +
>> + if (ev == event)
>> + continue;
>> + x86_perf_event_update(event);
>
> if (ev != event)
> x86_perf_event_update(event)
>> + }
>> +}
>> +
>> /*
>> * Save and restart an expired event. Called by NMI contexts,
>> * so it has to be careful about preempting normal event ops:
>> */
>> int intel_pmu_save_and_restart(struct perf_event *event)
>> {
>> + struct hw_perf_event *hwc = &event->hw;
>> +
>> + if (unlikely(hwc->reg_idx == INTEL_PMC_IDX_FIXED_SLOTS))
>> + intel_pmu_update_metrics(event);
>> +
>> x86_perf_event_update(event);
>> /*
>> * For a checkpointed counter always reset back to 0. This
>> --
>> 2.14.5
>>

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