lkml.org 
[lkml]   [2019]   [May]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH 2/5] ARM: dts: exynos: Add array of generic PHYs to EHCI/OHCI devices
Date
Add a standard array of PHYs to Exynos EHCI/OHCI devices. This is a first
step in resolving the conflict between Exynos EHCI/OHCI sub-nodes and
generic USB device bindings. Later the sub-nodes currently used for
assigning PHYs to root ports of the controller will be removed making
a place for the generic USB device bindings nodes.

Suggested-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/boot/dts/exynos4.dtsi | 4 ++++
arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 ++
arch/arm/boot/dts/exynos4412-itop-elite.dts | 2 ++
arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 ++
arch/arm/boot/dts/exynos4412-odroidx.dts | 2 ++
arch/arm/boot/dts/exynos4412-origen.dts | 2 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++++
arch/arm/boot/dts/exynos54xx.dtsi | 4 ++++
8 files changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 36ccf227434d..7b94fbd9ed6c 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -380,6 +380,8 @@
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
+ phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
+ phy-names = "host", "hsic0", "hsic1";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
@@ -406,6 +408,8 @@
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
+ phys = <&exynos_usbphy 1>;
+ phy-names = "host";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index bf092e97e14f..dbd6b43dbe52 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -204,6 +204,8 @@

&ehci {
status = "okay";
+ phys = <&exynos_usbphy 1>;
+ phy-names = "host";
port@0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
index 0dedeba89b5f..1763b42c01cb 100644
--- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -146,6 +146,8 @@
/* In order to reset USB ethernet */
samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;

+ phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>;
+ phy-names = "host", "hsic1";
port@0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index 96d99887bceb..5bbaccffc9be 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -105,6 +105,8 @@
};

&ehci {
+ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
+ phy-names = "hsic0", "hsic1";
port@1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index a2251581f6b6..306dd9365a91 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -72,6 +72,8 @@
};

&ehci {
+ phys = <&exynos_usbphy 2>;
+ phy-names = "hsic0";
port@1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 698de4345d16..e609e2af22d1 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -88,6 +88,8 @@
&ehci {
samsung,vbus-gpio = <&gpx3 5 1>;
status = "okay";
+ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
+ phy-names = "hsic0", "hsic1";

port@1 {
status = "okay";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index d5e0392b409e..2d23e99985e1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -617,6 +617,8 @@

clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
+ phys = <&usb2_phy_gen 1>;
+ phy-names = "host";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
@@ -632,6 +634,8 @@

clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
+ phys = <&usb2_phy_gen 1>;
+ phy-names = "host";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index ae866bcc30c4..ab1642cf0428 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -180,6 +180,8 @@
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy 1>;
+ phy-names = "host";

#address-cells = <1>;
#size-cells = <0>;
@@ -193,6 +195,8 @@
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy 1>;
+ phy-names = "host";

#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
\
 
 \ /
  Last update: 2019-05-21 14:03    [W:0.076 / U:5.940 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site