Messages in this thread |  | | Date | Tue, 21 May 2019 20:50:28 -0700 | From | Bjorn Andersson <> | Subject | Re: [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus |
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On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:
> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement > the same microarchitecture and the two clusters only differ in the > maximum frequency attainable by the CPUs. > > Add capacity-dmips-mhz property to allow the topology code to determine > the actual capacity by taking into account the highest frequency for > each CPU. > > Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> > Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Applied
Regards, Bjorn
> --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 4f2fb7885f39..e0e8f30ce11a 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -96,6 +96,7 @@ > reg = <0x0 0x0>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_0>; > L2_0: l2-cache { > compatible = "cache"; > @@ -109,6 +110,7 @@ > reg = <0x0 0x1>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_0>; > }; > > @@ -118,6 +120,7 @@ > reg = <0x0 0x100>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_1>; > L2_1: l2-cache { > compatible = "cache"; > @@ -131,6 +134,7 @@ > reg = <0x0 0x101>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_1>; > }; > > -- > 2.17.1 >
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