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SubjectRe: [PATCH 2/2] add dts file to enable support for ls1046afrwy board.
On Wed, May 08, 2019 at 01:53:10PM +0000, Pramod Kumar wrote:
> ls1046afrwy board is based on nxp ls1046a SoC.
>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>

Please have a subject prefix like 'arm64: dts: ...'

Shawn

> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/fsl-ls1046a-frwy.dts | 156 ++++++++++++++++++
> 2 files changed, 157 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 13604e558dc1..84ff6995b41e 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
> new file mode 100644
> index 000000000000..de0d19c02944
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
> + *
> + * Copyright 2019 NXP.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-ls1046a.dtsi"
> +
> +/ {
> + model = "LS1046A FRWY Board";
> + compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
> +
> + aliases {
> + serial0 = &duart0;
> + serial1 = &duart1;
> + serial2 = &duart2;
> + serial3 = &duart3;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + sb_3v3: regulator-sb3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT8642SEV-3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> +
> +&duart1 {
> + status = "okay";
> +};
> +
> +&duart2 {
> + status = "okay";
> +};
> +
> +&duart3 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + i2c-mux@77 {
> + compatible = "nxp,pca9546";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-never-disable;
> +
> + i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + eeprom@52 {
> + compatible = "atmel,24c512";
> + reg = <0x52>;
> + };
> +
> + eeprom@53 {
> + compatible = "atmel,24c512";
> + reg = <0x53>;
> + };
> +
> + power-monitor@40 {
> + compatible = "ti,ina220";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> +
> + rtc@51 {
> + compatible = "nxp,pcf2129";
> + reg = <0x51>;
> + };
> +
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <&sb_3v3>;
> + };
> +
> + };
> + };
> +};
> +
> +&ifc {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + /* NAND Flash */
> + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
> + status = "okay";
> +
> + nand@0,0 {
> + compatible = "fsl,ifc-nand";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0 0x0 0x10000>;
> + };
> +
> +};
> +
> +#include "fsl-ls1046-post.dtsi"
> +
> +&fman0 {
> + ethernet@e0000 {
> + phy-handle = <&qsgmii_phy4>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + ethernet@e8000 {
> + phy-handle = <&qsgmii_phy2>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + ethernet@ea000 {
> + phy-handle = <&qsgmii_phy1>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + ethernet@f2000 {
> + phy-handle = <&qsgmii_phy3>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + mdio@fd000 {
> + qsgmii_phy1: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + qsgmii_phy2: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + qsgmii_phy3: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + qsgmii_phy4: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> +};
> --
> 2.17.1

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