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SubjectRe: [PATCH] mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG
Hi Jeff,

On 14.05.19 17:42, Jeff Kletsky wrote:
> On 5/13/19 6:56 AM, Schrempf Frieder wrote:
>> Hi Jeff,
>> I just noticed I hit the wrong button and my previous reply was only
>> sent to the MTD list, so I'm resending with fixed recipients...
>> On 10.05.19 14:17, wrote:
>>> From: Jeff Kletsky<>
>>> The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
>>> and, while it has the same logical layout as the E-series devices,
>>> it differs in the SPI interfacing in significant ways.
>>> To accommodate these changes, this patch also:
>>> * Adds support for two-byte manufacturer IDs
>>> * Adds #define-s for three-byte addressing for read ops
>>> Signed-off-by: Jeff Kletsky<>
>> Maybe it would be better to split this patch into three parts:
>> * Add support for two-byte device IDs
>> * Add #define-s for three-byte addressing for read ops
>> * Add support for GD5F1GQ4UFxxG
>> Anyway the content looks good to me, so:
>> Reviewed-by: Frieder Schrempf<>
>> [...]
> Thanks for the time in review and good words!

You're welcome!

> My apologies for an incomplete git-send-email config that left
> me nameless in the headers.

No problem, I guessed your name from the Signed-off-by tag ;)

> I wasn't sure if that was direction to submit as three patches
> at this time, but would be happy to do so if the consensus is
> that it the direction to follow.

I think it's common to separate logical different changes. This makes it
easier to read.
Also the preparation changes only touch the SPI NAND core. I guess
that's another reason why they should be separated from the
chip-specific changes.

> At least for me, I feel that the other two don't really stand
> on their own without the context for their need.

I don't think that's a problem. Just add a note to the commit message
that these core changes are needed to prepare for the GD5F1GQ4UFxxG support.

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