lkml.org 
[lkml]   [2019]   [Apr]   [8]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRE: [PATCH v2] RISC-V: Implement ASID allocator
Date


> -----Original Message-----
> From: Guo Ren <guoren@kernel.org>
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel <Anup.Patel@wdc.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>; Albert Ou
> <aou@eecs.berkeley.edu>; linux-kernel@vger.kernel.org; Mike Rapoport
> <rppt@linux.ibm.com>; Christoph Hellwig <hch@infradead.org>; Atish Patra
> <Atish.Patra@wdc.com>; Gary Guo <gary@garyguo.net>; Paul Walmsley
> <paul.walmsley@sifive.com>; linux-riscv@lists.infradead.org
> Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator
>
> Hi Anup,
>
> On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote:
> > This patch is tested on QEMU/virt machine and SiFive Unleashed board.
> > On QEMU/virt machine, we see 10% (approx) performance improvement
> with
> > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP
> > CSR are not implemented on SiFive Unleashed board so we don't see any
> > change in performance.
> Can you tell me what is the test case ?

I am testing this using hackbench.

Regards,
Anup

\
 
 \ /
  Last update: 2019-04-09 05:37    [W:0.091 / U:3.076 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site