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SubjectRe: [PATCH v2 18/25] drm/mediatek: add RDMA fifo size error handle
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On Tue, 2019-04-16 at 16:00 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Wed, 2019-03-27 at 14:19 +0800, yongqiang.niu@mediatek.com wrote:
> > From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >
> > This patch add RDMA fifo size error handle
> > rdma fifo size will not always bigger than the calculated threshold
> > if that case happened, we need set fifo size as the threshold
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index b0a5cff..ead38ba 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -137,11 +137,14 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > {
> > unsigned int threshold;
> > unsigned int reg;
> > + unsigned int rdma_fifo_size;
> > struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> >
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> >
> > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
> > +
> > /*
> > * Enable FIFO underflow since DSI and DPI can't be blocked.
> > * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> > @@ -149,8 +152,12 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > * account for blanking, and with a pixel depth of 4 bytes:
> > */
> > threshold = width * height * vrefresh * 4 * 7 / 1000000;
> > +
> > + if (threshold > rdma_fifo_size)
> > + threshold = rdma_fifo_size;
>
> I think this is a work around not a correct solution. Why MT8173 has no
> this problem but MT8183 has? Is the formula of threshold different in
> MT8173 and MT8183?
>
> Regards,
> CK
>

fifo size of RDMA0 and RDMA1 in MT8173 are same, which is SZ_8K.
this formula calculate result will not overflow if the screen size is
not big enough.

but fifo size of RDMA1 in MT8183 only SZ_2K, if RDMA1 display with
solution 1080p60hz, this formula calculate result 3483 will overflow
SZ_2K.

> > +
> > reg = RDMA_FIFO_UNDERFLOW_EN |
> > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
> > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> > writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> > }
>
>


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