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Subject[PATCH] ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288
Date
The value was determined with the following method:

- take CPUs 1-3 offline
- for each OPP
- set cpufreq min and max freq to OPP freq
- start dhrystone benchmark
- measure CPU power consumption during 10s
- calculate Cx for OPPx
- Cx = (Px - P1) / (Vx²fx - V1²f1) [1]
using the following units: mW / Ghz / V [2]
- C = avg(C2, ..., Cn)

[1] see commit 4daa001a1773 ("arm64: dts: juno: Add cpu
dynamic-power-coefficient information")
[2] https://patchwork.kernel.org/patch/10493615/#22158551

FTR, these are the values for the different OPPs:

freq (kHz) mV Px (mW) Cx

126000 900 39
216000 900 66 370
312000 900 95 372
408000 900 122 363
600000 900 177 359
696000 950 230 363
816000 1000 297 361
1008000 1050 404 362
1200000 1100 528 362
1416000 1200 770 377
1512000 1300 984 385
1608000 1350 1156 394

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
---
I couldn't find any really comprehensive information on determining
the dynamic-power-coefficient, the method used is my understanding
mostly derived from the sources mentioned above, the resulting value
is within a reasonable range and the range of the intermediate Cx
values is consistent. If someone knows better and things should be
done differently please share your knowledge :)
---
arch/arm/boot/dts/rk3288.dtsi | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 23e9c5253019..f0d92b045c57 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -61,6 +61,7 @@
reg = <0x500>;
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu_opp_table>;
+ dynamic-power-coefficient = <370>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@@ -71,6 +72,7 @@
reg = <0x501>;
resets = <&cru SRST_CORE1>;
operating-points = <&cpu_opp_table>;
+ dynamic-power-coefficient = <370>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@@ -81,6 +83,7 @@
reg = <0x502>;
resets = <&cru SRST_CORE2>;
operating-points = <&cpu_opp_table>;
+ dynamic-power-coefficient = <370>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@@ -91,6 +94,7 @@
reg = <0x503>;
resets = <&cru SRST_CORE3>;
operating-points = <&cpu_opp_table>;
+ dynamic-power-coefficient = <370>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
--
2.21.0.392.gf8f6787159e-goog
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