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SubjectRe: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
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Quoting Weiyi Lu (2019-03-04 21:05:40)
> From: Owen Chen <owen.chen@mediatek.com>
>
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> add a variable to indicate this change and
> backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
> 1.5Ghz, add a variable to indicate platform-dependent.
>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Acked-by: Sean Wang <sean.wang@kernel.org>
> ---

Applied to clk-next

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