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SubjectRe: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake
Date
On 2019/4/8 8:03 PM, Thomas Gleixner wrote:
> On Mon, 8 Apr 2019, You-Sheng Yang wrote:
>> + /*
>> + * On Intel CoffeeLake, tsc may be marked unstable unexpectedly after
>> + * entering PC10.
>> + */
>> + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
>> + (boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_MOBILE ||
>> + boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_DESKTOP) &&
>> + boot_cpu_data.x86_stepping >= 0x0a)
>> + tsc_clocksource_reliable = 1;
>
> No. We are not starting that family/model/stepping game especially not
> with random stepping cutoffs which are pulled out of thin air. That's
> going to spiral out of control sooner than later.

What about we simply disable clocksource watchdog if this is an
invariant TSC?

> There must be a better way to do that. Rafael?
>
> Thanks,
>
> tglx

You-Sheng Yang

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