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Subject[PATCH 2/2] dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY
Date
Add bindings to describe Mediatek MT7621 PCIe PHY.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
.../bindings/phy/mediatek,mt7621-pci-phy.txt | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt
new file mode 100644
index 000000000000..8addedbe815e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt
@@ -0,0 +1,54 @@
+Mediatek Mt7621 PCIe PHY
+
+Required properties:
+- compatible: must be "mediatek,mt7621-pci-phy"
+- reg: base address and length of the PCIe PHY block
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Each PCIe PHY should be represented by a child node
+
+Required properties For the child node:
+- reg: the PHY ID
+0 - PCIe RC 0
+1 - PCIe RC 1
+- #phy-cells: must be 0
+
+Example:
+ pcie0_phy: pcie-phy@1e149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e149000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie0_port: pcie-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ pcie1_port: pcie-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ pcie1_phy: pcie-phy@1e14a000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e14a000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie2_port: pcie-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ /* users of the PCIe phy */
+
+ pcie: pcie@1e140000 {
+ ...
+ ...
+ phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ };
--
2.19.1
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