[lkml]   [2019]   [Mar]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
Subject[PATCH 0/2] clk: keystone: Add new driver to handle syscon based clock
On TI's K2 and K3 SoCs, certain clocks can be gated/ungated by setting a
single bit in SoC's System Control registers. Sometime more than
one clock control can be in the same register. But these registers might
also have bits to control other SoC functionalities.
For example, Time Base clock(tbclk) enable bits for various EPWM IPs are
all in EPWM_CTRL Syscon registers on K2G SoC.

This series adds a new clk driver to support such clocks. Registers
which control clocks will be grouped into a syscon DT node, thus
enabling sharing of register across clk drivers and other drivers.
Each clock node will be child of the syscon node describing offset and
bit within the regmap that controls the clock output.

Vignesh Raghavendra (2):
dt-bindings: clock: Add binding documentation for TI syscon gate clock
clk: keystone: Add new driver to handle syscon based clock

.../bindings/clock/ti,syscon-gate-clock.txt | 35 +++++
drivers/clk/keystone/Kconfig | 8 +
drivers/clk/keystone/Makefile | 1 +
drivers/clk/keystone/syscon-clk.c | 143 ++++++++++++++++++
4 files changed, 187 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt
create mode 100644 drivers/clk/keystone/syscon-clk.c


 \ /
  Last update: 2019-03-12 10:05    [W:0.090 / U:2.284 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site