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SubjectRe: [PATCH v3 09/10] x86/split_lock: Define #AC for split lock feature
On Mon, Feb 04, 2019 at 11:00:03AM -0800, Dave Hansen wrote:
> On 2/4/19 10:45 AM, Fenghua Yu wrote:
> > On Mon, Feb 04, 2019 at 10:41:40AM -0800, Dave Hansen wrote:
> >> On 2/1/19 9:14 PM, Fenghua Yu wrote:
> >>> --- a/arch/x86/include/asm/cpufeatures.h
> >>> +++ b/arch/x86/include/asm/cpufeatures.h
> >>> @@ -221,6 +221,7 @@
> >>> #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
> >>> #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
> >>> #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
> >>> +#define X86_FEATURE_AC_SPLIT_LOCK ( 7*32+31) /* #AC for split lock */
> >>
> >> The last time this was posted, we (Intel) promised to go get the proper
> >> (CPUID or MSR-based) enumeration of this feature documented. Did we do
> >> that? If so, where is that documentation?
> >
> > As said in the cover patch:
> > "Please note: The feature could be enumerated through
> > MSR IA32_CORE_CAPABILITY (0xCF). But the enumeration is not completely
> > published yet. So this patch set doesn't include the method."
>
> FWIW, I think we (Intel) promised to get this documented _before_ we
> came back asking our intrepid x86 maintainers to accept something like
> setcpuid=. While I generally applaud the post-early-post-often
> attitude, we might have been a bit trigger-happy on this one.
>
> This is awfully crucial information to bury in a massive cover letter,
> especially when the patch description is a rather anemic two lines.
>
Hi, Dave,

I do have two pathes available to enumerate IA32_CORE_CAPABILITY itself
and to enumerate #AC for split lock by bit 5 in the MSR. But because the
enumeration for the MSR is not published, I cannot release the two
patches in this patch set.

Hopefully this patch set without the two enumeration patches is
a meaningful set.

Thanks.

-Fenghua

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