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SubjectRe: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
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On 26/02/2019 07:59, Bjorn Andersson wrote:

> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 7 +
> drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp.h | 12 ++
> 3 files changed, 179 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> index 5d181fc3cc18..dd2725a9d3f7 100644
> --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> @@ -11,6 +11,7 @@ Required properties:
> "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
> "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
> "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
> + "qcom,sdm845-qmp-pcie-phy" for PCIe phy on sdm845,
> "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
> "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
> "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
> @@ -48,6 +49,10 @@ Required properties:
> "aux", "cfg_ahb", "ref".
> For "qcom,msm8998-qmp-ufs-phy" must contain:
> "ref", "ref_aux".
> + For "qcom,sdm845-qmp-usb3-phy" must contain:
> + "aux", "cfg_ahb", "ref", "refgen".

qcom,sdm845-qmp-usb3-phy in a PCIe patch?

> + For "qcom,sdm845-qmp-usb3-phy" must contain:
> + "aux", "cfg_ahb", "ref", "com_aux".

qcom,sdm845-qmp-usb3-phy again in a PCIe patch?


> +static const struct qmp_phy_init_tbl sdm845_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};

I was thinking I might need to do the same for msm8998, since downstream
tweaks pcs_misc + 0x2c = 0x52
(dunno if that's QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2)

The thing is, phy driver writes unconditionally to pcs_misc + 0x0c
(QPHY_V3_PCS_MISC_CLAMP_ENABLE). Should that be moved elsewhere?

Regards.

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