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SubjectRe: [PATCH v2] clk: imx: Refactor entire sccg pll clk
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Quoting Abel Vesa (2019-02-23 02:58:14)
> On 19-02-22 09:46:23, Stephen Boyd wrote:
> > Quoting Abel Vesa (2019-02-22 09:07:32)
> > > Make the entire combination of plls to be one single clock. The parents used
> > > for bypasses are specified each as an index in the parents list.
> > > The determine_rate does a lookup throughout all the possible combinations
> > > for all the divs and returns the best possible 'setup' which in turn is used
> > > by set_rate later to set up all the divs and bypasses.
> > >
> > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > > Tested-by: Lucas Stach <l.stach@pengutronix.de>
> > > Acked-by: Lucas Stach <l.stach@pengutronix.de>
> >
> > I suspect these tested by and acked tags should have been dropped,
> > unless you discussed and tested off-list?
> >
>
> Oups, I forgot to drop them.

Ok. Can Lucas re-test?

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