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SubjectRe: [PATCH v5 6/6] clk: renesas: r8a774c0: Add Z2 clock
On Mon, Feb 11, 2019 at 02:58:58PM +0100, Simon Horman wrote:
> Adds support for R-Car RZ/G2E (r8a774c0) Z2 clock.

R-Car should not appear on the line above.

>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3: New patch
> ---
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index 10b96895d452..24634ca94f69 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
> /* Core Clock Outputs */
> DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
> DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
> + DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4, 8),
> DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
> DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
> DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
> --
> 2.11.0
>

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