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Subject[PATCH 3/3] phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver
Date
For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's
P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the
P_ENABLE bits of the same register are set to P_ENABLE instead of
P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable
the lane as needed. The DisplayPort mode is selected according to
lane<n>-mode -property. All other values of lane<n>-mode -property but
PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to
force enable.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
drivers/phy/ti/phy-j721e-wiz.c | 55 +++++++++++++++++++++++++++++++---
1 file changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index c74979655654..d2a38ea6d881 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -20,6 +20,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
+#include <dt-bindings/phy/phy.h>

#define WIZ_SERDES_CTRL 0x404
#define WIZ_SERDES_TOP_CTRL 0x408
@@ -78,6 +79,8 @@ static const struct reg_field p_enable[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 30, 31),
};

+enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
+
static const struct reg_field p_align[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(0), 29, 29),
REG_FIELD(WIZ_LANECTL(1), 29, 29),
@@ -220,6 +223,7 @@ struct wiz {
struct reset_controller_dev wiz_phy_reset_dev;
struct gpio_desc *gpio_typec_dir;
int typec_dir_delay;
+ u32 lane_modes[WIZ_MAX_LANES];
};

static int wiz_reset(struct wiz *wiz)
@@ -242,12 +246,17 @@ static int wiz_reset(struct wiz *wiz)
static int wiz_mode_select(struct wiz *wiz)
{
u32 num_lanes = wiz->num_lanes;
+ enum wiz_lane_standard_mode mode;
int ret;
int i;

for (i = 0; i < num_lanes; i++) {
- ret = regmap_field_write(wiz->p_standard_mode[i],
- LANE_MODE_GEN4);
+ if (wiz->lane_modes[i] == PHY_TYPE_DP)
+ mode = LANE_MODE_GEN1;
+ else
+ mode = LANE_MODE_GEN4;
+
+ ret = regmap_field_write(wiz->p_standard_mode[i], mode);
if (ret)
return ret;
}
@@ -713,7 +722,7 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
return ret;
}

- ret = regmap_field_write(wiz->p_enable[id - 1], false);
+ ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
return ret;
}

@@ -740,7 +749,11 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
return ret;
}

- ret = regmap_field_write(wiz->p_enable[id - 1], true);
+ if (wiz->lane_modes[id - 1] == PHY_TYPE_DP)
+ ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
+ else
+ ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
+
return ret;
}

@@ -767,6 +780,33 @@ static const struct of_device_id wiz_id_table[] = {
};
MODULE_DEVICE_TABLE(of, wiz_id_table);

+static int wiz_get_lane_mode(struct device *dev, int lane_number,
+ u32 *lane_mode)
+{
+ char property_name[11]; /* 11 is length of "lane0-mode\0" */
+ int ret;
+
+ ret = snprintf(property_name, sizeof(property_name), "lane%u-mode",
+ lane_number);
+
+ if (ret != 10) { /* 10 is length of "lane0-mode" */
+ dev_err(dev, "%s: bad lane number %d (ret = %d)\n",
+ __func__, lane_number, ret);
+ return -ENOTSUPP;
+ }
+
+ ret = of_property_read_u32(dev->of_node, property_name, lane_mode);
+ if (ret == -EINVAL) {
+ *lane_mode = PHY_NONE;
+ return 0;
+ } else if (ret) {
+ dev_err(dev, "Getting \"%s\" property failed: %d\n",
+ property_name, ret);
+ }
+
+ return ret;
+}
+
static int wiz_probe(struct platform_device *pdev)
{
struct reset_controller_dev *phy_reset_dev;
@@ -780,6 +820,7 @@ static int wiz_probe(struct platform_device *pdev)
struct wiz *wiz;
u32 num_lanes;
int ret;
+ int i;

wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
if (!wiz)
@@ -850,6 +891,12 @@ static int wiz_probe(struct platform_device *pdev)
}
}

+ for (i = 0; i < num_lanes; i++) {
+ ret = wiz_get_lane_mode(dev, i, &wiz->lane_modes[i]);
+ if (ret)
+ return ret;
+ }
+
wiz->dev = dev;
wiz->regmap = regmap;
wiz->num_lanes = num_lanes;
--
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