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SubjectRe: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt
On 12/9/19 3:30 PM, John Garry wrote:
> On 07/12/2019 08:03, Ming Lei wrote:
>> On Fri, Dec 06, 2019 at 10:35:04PM +0800, John Garry wrote:
>>> Currently the cpu allowed mask for the threaded part of a threaded irq
>>> handler will be set to the effective affinity of the hard irq.
>>> Typically the effective affinity of the hard irq will be for a single
>>> cpu. As such,
>>> the threaded handler would always run on the same cpu as the hard irq.
>>> We have seen scenarios in high data-rate throughput testing that the cpu
>>> handling the interrupt can be totally saturated handling both the hard
>>> interrupt and threaded handler parts, limiting throughput.
> Hi Ming,
>> Frankly speaking, I never observed that single CPU is saturated by one
>> storage
>> completion queue's interrupt load. Because CPU is still much quicker than
>> current storage device.
>> If there are more drives, one CPU won't handle more than one
>> queue(drive)'s
>> interrupt if (nr_drive * nr_hw_queues) < nr_cpu_cores.
> Are things this simple? I mean, can you guarantee that fio processes are
> evenly distributed as such?
I would assume that it does, seeing that that was the primary goal of
fio ...

>> So could you describe your case in a bit detail? Then we can confirm
>> if this change is really needed.
> The issue is that the CPU is saturated in servicing the hard and
> threaded part of the interrupt together - here's the sort of thing which
> we saw previously:
> Before:
> CPU    %usr    %sys    %irq    %soft    %idle
> all    2.9    13.1    1.2    4.6    78.2
> 0    0.0    29.3    10.1    58.6    2.0
> 1    18.2    39.4    0.0    1.0    41.4
> 2    0.0    2.0    0.0    0.0    98.0
> CPU0 has no effectively no idle.
> Then, by allowing the threaded part to roam:
> After:
> CPU    %usr    %sys    %irq    %soft    %idle
> all    3.5    18.4    2.7    6.8    68.6
> 0    0.0    20.6    29.9    29.9    19.6
> 1    0.0    39.8    0.0    50.0    10.2
> Note: I think that I may be able to reduce the irq hard part load in the
> endpoint driver, but not that much such that we see still this issue.
Well ... to get a _real_ comparison you would need to specify the number
of irqs handled (and the resulting IOPS) alongside the cpu load.
It might well be that by spreading out the interrupts to other CPUs
we're increasing the latency, thus trivially reducing the load ...

My idea here is slightly different: can't we leverage SMT?
Most modern CPUs do SMT (I guess even ARM does it nowadays)
(Yes, I know about spectre and things. We're talking performance here :-)

So for 2-way SMT one could move the submisson queue on one side, and the
completion queue handling (ie the irq handling) on the other side.
Due to SMT we shouldn't suffer from cache misses (keep fingers crossed),
and might even get better performance.

John, would such a scenario work on your boxes?
IE can we tweak the interrupt and queue assignment?

Initially I would love to test things out, just to see what'll be
happening; might be that it doesn't bring any benefit at all, but it'd
be interesting to test out anyway.


Dr. Hannes Reinecke Teamlead Storage & Networking +49 911 74053 688
SUSE Software Solutions GmbH, Maxfeldstr. 5, 90409 Nürnberg
HRB 36809 (AG Nürnberg), Geschäftsführer: Felix Imendörffer

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