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SubjectAbout DT binding of reset control
Hello, Rob, DT folks,

I am trying to add the reset control into
the Denali NAND controller driver:

I'd like to get some advice about the DT binding
before the detailed implementation.

The IP datasheet clearly says
two separate reset lines, like this:

rst_n : controller core reset
reg_rst_n: register flip-flop reset

But, in actual SoC integration,
the two reset signals are often tied up together, and
the reset controller only provides 1-bit control.

(The upstream platforms, SoCFPGA, UniPhier,
both are this case.)

In this case, which is more preferred for the
DT binding?

[1] Define two resets explicitly according to the IP spec

Optional properties:
reset-names : contain "nand", "reg"
resets: phandles to the controller core reset, the register reset


nand {
reset-names = "nand", "reg";
resets = <&nand_rst>, <&nand_rst>;

[2] Allow arbitrary number of reset lines

Optional properties:
resets: phandle(s) to reset(s)

The number of reset lines is SoC-dependent.


nand {

resets = <&nand>;

I guess [1] is more precise as the hardware specification.
But, DT files will end up with giving the same phandle
to both of the two resets.
I think it is OK, but anyway better to ask
before proceeding.


Best Regards
Masahiro Yamada

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