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    Subject[PATCH 5.4 159/434] drm/amd/display: fix header for RN clk mgr
    Date
    From: joseph gravenor <joseph.gravenor@amd.com>

    [ Upstream commit cd83fa1ea9b9431cf1d57ac4179a11bc4393a5b6 ]

    [why]
    Should always MP0_BASE for any register definition from MP per-IP header files.
    I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table
    of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file.
    The reason we should only use MP0_BASE is There is only one set of per-IP headers MP
    that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2
    and an ecryption engine that can be used only by MP0. As a result all register definitions from
    MP file should be based only on MP0_BASE data.

    [How]
    Change MP1_BASE to MP0_BASE

    Signed-off-by: joseph gravenor <joseph.gravenor@amd.com>
    Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
    Reviewed-by: Roman Li <Roman.Li@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
    index 50984c1811bb..468c6bb0e311 100644
    --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
    +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
    @@ -33,7 +33,7 @@
    #include "mp/mp_12_0_0_sh_mask.h"

    #define REG(reg_name) \
    - (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
    + (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

    #define FN(reg_name, field) \
    FD(reg_name##__##field)
    --
    2.20.1


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