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Subject[PATCH 0/3] A64/H3/H6 R_CCU clock fixes
Hi all,

I was examining the H6 BSP clock driver[1] for guidance when porting an
AR100 firmware[2] to the H6 SoC. I found some inconsistencies between
that code and the sunxi-ng driver.

I don't have a good way to verify the first patch. Someone with an
oscilloscope could set the divider and check the I2C/RSB frequency.

Patch 2 should have no functional change.

Patch 3 was verified by benchmarking. Details are in the commit message.


Samuel Holland (3):
clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition
clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order

drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 16 +++-------------
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 21 +++------------------
2 files changed, 6 insertions(+), 31 deletions(-)


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