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SubjectRe: [PATCH v2 2/2] arm64: dts: realtek: Add RTD1319 SoC and Realtek PymParticle EVB
On 2019-12-28 15:05, James Tai wrote:
> Add Device Trees for Realtek RTD1319 SoC family, RTD1319 SoC and
> Realtek PymParticle EVB.
>
> Signed-off-by: James Tai <james.tai@realtek.com>
> ---
> arch/arm64/boot/dts/realtek/Makefile | 2 +
> .../boot/dts/realtek/rtd1319-pymparticle.dts | 43 ++++
> arch/arm64/boot/dts/realtek/rtd1319.dtsi | 12 +
> arch/arm64/boot/dts/realtek/rtd13xx.dtsi | 212 ++++++++++++++++++
> 4 files changed, 269 insertions(+)
> create mode 100644 arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts
> create mode 100644 arch/arm64/boot/dts/realtek/rtd1319.dtsi
> create mode 100644 arch/arm64/boot/dts/realtek/rtd13xx.dtsi
>
> diff --git a/arch/arm64/boot/dts/realtek/Makefile
> b/arch/arm64/boot/dts/realtek/Makefile
> index ef8d8fcbaa05..c0ae96f324eb 100644
> --- a/arch/arm64/boot/dts/realtek/Makefile
> +++ b/arch/arm64/boot/dts/realtek/Makefile
> @@ -9,6 +9,8 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
>
> dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
>
> +dtb-$(CONFIG_ARCH_REALTEK) += rtd1319-pymparticle.dtb
> +
> dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
> dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts
> b/arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts
> new file mode 100644
> index 000000000000..2a36d220fef6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2019 Realtek Semiconductor Corp.
> + */
> +
> +/dts-v1/;
> +
> +#include "rtd1319.dtsi"
> +
> +/ {
> + compatible = "realtek,pymparticle", "realtek,rtd1319";
> + model = "Realtek PymParticle EVB";
> +
> + memory@2e000 {
> + device_type = "memory";
> + reg = <0x2e000 0x3ffd2000>; /* boot ROM to 1 GiB or 2 GiB */
> + };
> +
> + chosen {
> + stdout-path = "serial0:460800n8";
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + };
> +};
> +
> +/* debug console (J1) */
> +&uart0 {
> + status = "okay";
> +};
> +
> +/* M.2 slot (CON8) */
> +&uart1 {
> + status = "disabled";
> +};
> +
> +/* GPIO connector (T1) */
> +&uart2 {
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/realtek/rtd1319.dtsi
> b/arch/arm64/boot/dts/realtek/rtd1319.dtsi
> new file mode 100644
> index 000000000000..1dcee00009cd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/realtek/rtd1319.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +/*
> + * Realtek RTD1319 SoC
> + *
> + * Copyright (c) 2019 Realtek Semiconductor Corp.
> + */
> +
> +#include "rtd13xx.dtsi"
> +
> +/ {
> + compatible = "realtek,rtd1319";
> +};
> diff --git a/arch/arm64/boot/dts/realtek/rtd13xx.dtsi
> b/arch/arm64/boot/dts/realtek/rtd13xx.dtsi
> new file mode 100644
> index 000000000000..18d063feaa7e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/realtek/rtd13xx.dtsi
> @@ -0,0 +1,212 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +/*
> + * Realtek RTD13xx SoC family
> + *
> + * Copyright (c) 2019 Realtek Semiconductor Corp.
> + */
> +
> +/memreserve/ 0x0000000000000000 0x000000000002e000; /* Boot ROM */
> +/memreserve/ 0x000000000002e000 0x0000000000100000; /* Boot loader */
> +/memreserve/ 0x000000000f400000 0x0000000000500000; /* Video FW */
> +/memreserve/ 0x000000000f900000 0x0000000000500000; /* Audio FW */
> +/memreserve/ 0x0000000010000000 0x0000000000014000; /* Audio FW RAM */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + rpc_comm: rpc@3f000 {
> + reg = <0x3f000 0x1000>;
> + };
> +
> + rpc_ringbuf: rpc@1ffe000 {
> + reg = <0x1ffe000 0x4000>;
> + };
> +
> + tee: tee@10100000 {
> + reg = <0x10100000 0xf00000>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x100>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x200>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x300>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache {
> + compatible = "cache";
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

Nit: At some point, it'd be good to be able to describe the EL2
virtual timer interrupt too. Not specially important, but since
these ARMv8.2 CPUs have it...

[...]

> + gic: interrupt-controller@ff100000 {
> + compatible = "arm,gic-v3";
> + reg = <0xff100000 0x10000>,
> + <0xff140000 0xc0000>;

Are you sure about the size of the GICR region? For 4 CPUs,
it should be 0x80000. Here, you have a range for 6 CPUs.

Has the GIC been sized for 6 CPUs? Are you missing 2 CPUs in
the DT?

M.
--
Jazz is not dead. It just smells funny...

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