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SubjectRe: [PATCH v2 1/1] net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs
From
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Thu, 26 Dec 2019 20:01:01 +0100

> GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for
> the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate
> can be adjusted at runtime.
>
> So far we have been running MPLL2 with ~250MHz (and the internal
> m250_div with value 1), which worked enough that we could transfer data
> with an TX delay of 4ns. Unfortunately there is high packet loss with
> an RGMII PHY when transferring data (receiving data works fine though).
> Odroid-C1's u-boot is running with a TX delay of only 2ns as well as
> the internal m250_div set to 2 - no lost (TX) packets can be observed
> with that setting in u-boot.
>
> Manual testing has shown that the TX packet loss goes away when using
> the following settings in Linux (the vendor kernel uses the same
> settings):
> - MPLL2 clock set to ~500MHz
> - m250_div set to 2
> - TX delay set to 2ns on the MAC side
>
> Update the m250_div divider settings to only accept dividers greater or
> equal 2 to fix the TX delay generated by the MAC.
>
> iperf3 results before the change:
> [ ID] Interval Transfer Bitrate Retr
> [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender
> [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver
>
> iperf3 results after the change (including an updated TX delay of 2ns):
> [ ID] Interval Transfer Bitrate Retr Cwnd
> [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender
> [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver
>
> Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Applied and queued up for -stable, thanks.

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