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Subject[PATCH v3 0/5] PCI: amlogic: Make PCIe working reliably on AXG platforms
PCIe device probing failures have been seen on AXG platforms and were due
to unreliable clock signal output. Setting HHI_MIPI_CNTL0[26] bit in
MIPI's PHY registers solved the problem. This bit appears to control band
gap reference.

As discussed here [1] one of these shared MIPI/PCIE PHY register bits was
mistakenly implemented in the clock driver as CLKID_MIPI_ENABLE. This adds
a PHY driver to control this bit through syscon subsystem instead, as well
as setting the band gap one in order to get reliable PCIE communication.

While at it adding this PHY make AXG code close to G12A one thus allowing
to remove some specific platform handling in pci-meson driver.

Please note that CLKID_MIPI_ENABLE removable will be done in a different

Changes since v2:
- Remove shared MIPI/PCIE device driver and use syscon to access register
in PCIE only driver instead
- Include devicetree documentation

Changes sinve v1:
- Move HHI_MIPI_CNTL0 bit control in its own PHY driver
- Add a PHY driver for PCIE_PHY registers
- Modify pci-meson.c to make use of both PHYs and remove specific
handling for AXG and G12A


Remi Pommarel (5):
phy: amlogic: Add Amlogic AXG PCIE PHY Driver
PCI: amlogic: Use AXG PCIE PHY
arm64: dts: meson-axg: Add PCIE PHY node
dt-bindings: PCI: meson: Update PCIE bindings documentation
dt-bindings: Add AXG PCIE PHY bindings

.../bindings/pci/amlogic,meson-pcie.txt | 22 +--
.../bindings/phy/amlogic,meson-axg-pcie.yaml | 51 +++++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 9 +
drivers/pci/controller/dwc/pci-meson.c | 116 ++---------
drivers/phy/amlogic/Kconfig | 11 ++
drivers/phy/amlogic/Makefile | 1 +
drivers/phy/amlogic/phy-meson-axg-pcie.c | 185 ++++++++++++++++++
7 files changed, 287 insertions(+), 108 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c


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