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Subject[PATCH v2 0/3] PCI: amlogic: Make PCIe working reliably on AXG platforms
PCIe device probing failures have been seen on AXG platforms and were due
to unreliable clock signal output. Setting HHI_MIPI_CNTL0[26] bit in
MIPI's PHY registers solved the problem. This bit controls band gap

As discussed here [1] one of these shared MIPI/PCIE PHY register bits was
implemented in the clock driver as CLKID_MIPI_ENABLE. This adds a PHY
driver to control this bit instead, as well as setting the band gap one
in order to get reliable PCIE communication.

While at it add another PHY driver to control PCIE only PHY registers,
making AXG code more similar to G12A platform thus allowing to remove
some specific platform handling in pci-meson driver.

Please note that devicetree and its documentation modifications as well as
CLKID_MIPI_ENABLE will be sent as different series if this one is
considered sane.

Changes sinve v1:
- Move HHI_MIPI_CNTL0 bit control in its own PHY driver
- Add a PHY driver for PCIE_PHY registers
- Modify pci-meson.c to make use of both PHYs and remove specific
handling for AXG and G12A


Remi Pommarel (3):
phy: amlogic: Add Amlogic AXG MIPI/PCIE PHY Driver
phy: amlogic: Add Amlogic AXG PCIE PHY Driver
PCI: amlogic: Use AXG PCIE and shared MIPI/PCIE PHYs

drivers/pci/controller/dwc/pci-meson.c | 140 +++++---------
drivers/phy/amlogic/Kconfig | 22 +++
drivers/phy/amlogic/Makefile | 2 +
drivers/phy/amlogic/phy-meson-axg-mipi-pcie.c | 176 ++++++++++++++++++
drivers/phy/amlogic/phy-meson-axg-pcie.c | 163 ++++++++++++++++
5 files changed, 409 insertions(+), 94 deletions(-)
create mode 100644 drivers/phy/amlogic/phy-meson-axg-mipi-pcie.c
create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c


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