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Subject[PATCH v2 0/2] at91-sama5d2_shdwc shutdown controller
PMC master clock register offset is different b/w sam9x60 and
other SoCs. Since there is a need of this register offset in
shutdown procedure we need to have it per SoC. This is what
this series does.

Changes in v2:
- do not use r5 as intermediary registers in at91_poweroff

Claudiu Beznea (2):
power: reset: at91-poweroff: introduce struct shdwc_reg_config
power: reset: at91-poweroff: use proper master clock register offset

drivers/power/reset/at91-sama5d2_shdwc.c | 72 +++++++++++++++++++++-----------
1 file changed, 47 insertions(+), 25 deletions(-)


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