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SubjectRe: [PATCH v7 06/12] dmaengine: ti: Add cppi5 header for K3 NAVSS/UDMA
On 09-12-19, 11:43, Peter Ujfalusi wrote:

> +#define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16)
> +#define CPPI5_INFO2_DESC_RETP_MASK GENMASK(18, 16)
> +
> +#define CPPI5_INFO2_DESC_RETQ_SHIFT (0)
> +#define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
> +
> +#define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U)
> +#define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
> +#define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0)
> +#define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)
> +
> +#define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT (0)
> +#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)
> +
> +#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT (0)
> +#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)

I think you can remove the SHIFT defines and use ffs() to get the bit
position for shift

> +static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
> + u32 sw_data_size)
> +{
> + u32 desc_size;
> +
> + if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
> + return 0;
> +
> + desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
> + sw_data_size;

I think there was an API for this kind of mem allocation of struct and
buffer attached...

> +static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
> +{
> + desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
> + desc->next_desc = 0;

would this not be superfluous? Or if you want a memset call?

> +static inline u32 *cppi5_hdesc_get_psdata32(struct cppi5_host_desc_t *desc)
> +{
> + return (u32 *)cppi5_hdesc_get_psdata(desc);

you dont need casts away from void *

--
~Vinod

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