lkml.org 
[lkml]   [2019]   [Dec]   [19]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents
From
Date
Quoting Lubomir Rintel (2019-12-18 11:04:54)
> Determined empirically, no documentation is available.
>
> The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
> thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
> what is going on, ended up just dividing the rate as of
> commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---

Any Fixes: tag?

Acked-by: Stephen Boyd <sboyd@kernel.org>

\
 
 \ /
  Last update: 2019-12-19 06:15    [W:0.055 / U:3.544 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site