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SubjectRe: [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses
On Thu, Dec 19, 2019 at 12:54 PM Kishon Vijay Abraham I <> wrote:
> Hi Andrew,
> On 16/12/19 8:19 pm, Andrew Murray wrote:
> > On Mon, Dec 09, 2019 at 02:51:39PM +0530, Kishon Vijay Abraham I wrote:
> >> Certain platforms like TI's J721E allow only 32-bit register accesses.
> >
> > When I first read this I thought you meant only 32-bit accesses are allowed
> > and not other sizes (such as 64-bit). However the limitation you address
> > here is that the J721E allows only 32-bit *aligned* register accesses.
> It's both, it allows only 32-bit aligned accesses and the size should be
> only 32 bits. That's why I always use "readl" in the APIs below.

In that case, can't you use the pci_generic_config_read32/write32
functions with a cadence specific .map_bus() function?


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