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SubjectRe: [PATCH 5/5] drm/msm/a6xx: Add support for using system cache(LLC)
On Thu, Dec 19, 2019 at 12:58:15PM -0700, Jordan Crouse wrote:
> On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:


<snip>

> > +
> > + /*
> > + * CNTL1 is used to specify SCID for (CP, TP, VFD, CCU and UBWC
> > + * FLAG cache) GPU blocks. This value will be passed along with
> > + * the address for any memory transaction from GPU to identify
> > + * the sub-cache for that transaction.
> > + */
> > + if (!IS_ERR(llc->gpu_llc_slice)) {
> > + u32 gpu_scid = llcc_get_slice_id(llc->gpu_llc_slice);
> > + int i;
> > +
> > + for (i = 0; i < A6XX_LLC_NUM_GPU_SCIDS; i++)
> > + llc->cntl1_regval |=
> > + gpu_scid << (A6XX_GPU_LLC_SCID_NUM_BITS * i);
>
> As above, i'm not sure a loop is better than just:
>
> gpu_scid &= 0x1f;
>
> llc->cntl1_regval = (gpu_scid << 0) || (gpu_scid << 5) | (gpu_scid << 10)
> | (gpu_scid << 15) | (gpu_scid << 20);
>
> And I'm not even sure we need do this math here in the first place.

One more question - can you get a valid slice id before activation?

<snip>

Jordan

--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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