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SubjectRe: [PATCH v2 19/36] irqchip/gic-v4.1: Add VPE INVALL callback
Date
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[Old email, doing some v3 cleanup]

On 2019-11-01 11:51, Zenghui Yu wrote:
> Hi Marc,
>
> On 2019/10/27 22:42, Marc Zyngier wrote:
>> GICv4.1 redistributors have a VPE-aware INVALL register. Progress!
>> We can now emulate a guest-requested INVALL without emiting a
>> VINVALL command.
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>
> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
>
>> ---
>> drivers/irqchip/irq-gic-v3-its.c | 14 ++++++++++++++
>> include/linux/irqchip/arm-gic-v3.h | 3 +++
>> 2 files changed, 17 insertions(+)
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c
>> b/drivers/irqchip/irq-gic-v3-its.c
>> index f7effd453729..10bd156aa042 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -3511,6 +3511,19 @@ static void its_vpe_4_1_deschedule(struct
>> its_vpe *vpe,
>> }
>> }
>> +static void its_vpe_4_1_invall(struct its_vpe *vpe)
>> +{
>> + void __iomem *rdbase;
>> + u64 val;
>> +
>> + val = GICR_INVLPIR_V;
>> + val |= FIELD_PREP(GICR_INVLPIR_VPEID, vpe->vpe_id);
>
> Can we use GICR_INVALL_V/VPEID instead, and ...
>
>> +
>> + /* Target the redistributor this vPE is currently known on */
>> + rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
>> + gic_write_lpir(val, rdbase + GICR_INVALLR);
>> +}
>> +
>> static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void
>> *vcpu_info)
>> {
>> struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
>> @@ -3526,6 +3539,7 @@ static int
>> its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
>> return 0;
>>
>> case INVALL_VPE:
>> + its_vpe_4_1_invall(vpe);
>> return 0;
>>
>> default:
>> diff --git a/include/linux/irqchip/arm-gic-v3.h
>> b/include/linux/irqchip/arm-gic-v3.h
>> index 6fd89d77b2b2..b69f60792554 100644
>> --- a/include/linux/irqchip/arm-gic-v3.h
>> +++ b/include/linux/irqchip/arm-gic-v3.h
>> @@ -247,6 +247,9 @@
>> #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
>> #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
>> +#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
>> +#define GICR_INVLPIR_V GENMASK_ULL(63, 63)
>> +
>
> ... define them here:
>
> #define GICR_INVALL_VPEID GICR_INVLPIR_VPEID
> #define GICR_INVALL_V GICR_INVLPIR_V

Yes, that's a sensible things to do. I'll squash that in my rebased
series.

Thanks,

M.
--
Jazz is not dead. It just smells funny...

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