Messages in this thread |  | | Subject | Re: [PATCH v8 02/10] iommu/vt-d: Add nested translation helper function | From | Lu Baolu <> | Date | Wed, 18 Dec 2019 10:41:53 +0800 |
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Hi again,
On 12/17/19 3:24 AM, Jacob Pan wrote: > +/** > + * intel_pasid_setup_nested() - Set up PASID entry for nested translation > + * which is used for vSVA. The first level page tables are used for > + * GVA-GPA or GIOVA-GPA translation in the guest, second level page tables > + * are used for GPA-HPA translation. > + * > + * @iommu: Iommu which the device belong to > + * @dev: Device to be set up for translation > + * @gpgd: FLPTPTR: First Level Page translation pointer in GPA > + * @pasid: PASID to be programmed in the device PASID table > + * @pasid_data: Additional PASID info from the guest bind request > + * @domain: Domain info for setting up second level page tables > + * @addr_width: Address width of the first level (guest) > + */ > +int intel_pasid_setup_nested(struct intel_iommu *iommu, > + struct device *dev, pgd_t *gpgd, > + int pasid, struct iommu_gpasid_bind_data_vtd *pasid_data, > + struct dmar_domain *domain, > + int addr_width) > +{ > + struct pasid_entry *pte; > + struct dma_pte *pgd; > + u64 pgd_val; > + int agaw; > + u16 did; > + > + if (!ecap_nest(iommu->ecap)) { > + pr_err("IOMMU: %s: No nested translation support\n", > + iommu->name); > + return -EINVAL; > + } > + > + pte = intel_pasid_get_entry(dev, pasid); > + if (WARN_ON(!pte)) > + return -EINVAL; > + > + pasid_clear_entry(pte);
In some cases, e.g. nested mode for GIOVA-HPA, the PASID entry might have already been setup for second level translation. (This could be checked with the Present bit.) Hence, it's safe to flush caches here.
Or, maybe intel_pasid_tear_down_entry() is more suitable?
Best regards, baolu
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