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SubjectRe: [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses
On Mon, Dec 09, 2019 at 02:51:39PM +0530, Kishon Vijay Abraham I wrote:
> Certain platforms like TI's J721E allow only 32-bit register accesses.
> Add read and write accessors to perform only 32-bit accesses in order to
> support platfroms like TI's J721E.

s/platfroms/platforms/

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/controller/cadence/pcie-cadence.c | 40 +++++++++++++++++++
> drivers/pci/controller/cadence/pcie-cadence.h | 2 +
> 2 files changed, 42 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
> index cd795f6fc1e2..de5b3b06f2d0 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence.c
> @@ -7,6 +7,46 @@
>
> #include "pcie-cadence.h"
>
> +u32 cdns_pcie_read32(void __iomem *addr, int size)
> +{
> + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
> + unsigned int offset = (unsigned long)addr & 0x3;
> + u32 val = readl(aligned_addr);
> +
> + if (!IS_ALIGNED((uintptr_t)addr, size)) {
> + pr_err("Invalid Address in function:%s\n", __func__);

It might be nice to have a hint about *why* it's invalid, e.g., the
addr and size values.

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