lkml.org 
[lkml]   [2019]   [Dec]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
On Mon, Dec 16, 2019 at 12:59:16AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The A10/A20 Allwinner SoCs have two camera sensor interface blocks,
> named CSI0 and CSI1. The two have the same register layouts with
> slightly different features:
>
> - CSI0 has an image signal processor (ISP); CSI1 doesn't
>
> - CSI0 can support up to four separate channels under CCIR656;
> CSI1 can only support one
>
> - CSI0 can support up to 16-bit wide bus with YUV422;
> CSI1 can support up to 24-bit wide bus with YUV444
>
> For now the driver doesn't support wide busses, nor CCIR656. So the
> only relevant difference is whether a clock needs to be taken and
> enabled for the ISP.
>
> Add structs to record the differences, tie them to the compatible
> strings, and deal with the ISP clock. Support for the new CSI1
> hardware block is added as well.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!
Maxime
[unhandled content-type:application/pgp-signature]
\
 
 \ /
  Last update: 2019-12-16 14:39    [W:0.152 / U:0.844 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site