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Subject[PATCH V2 3/6] dt-bindings: clk: sprd: add bindings for sc9863a clock controller
Date
From: Chunyan Zhang <chunyan.zhang@unisoc.com>

add a new bindings to describe sc9863a clock compatible string.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
.../bindings/clock/sprd,sc9863a-clk.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
new file mode 100644
index 000000000000..881f0a0287e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2019 Unisoc Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: SC9863A Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ compatible :
+ enum:
+ - sprd,sc9863a-ap-clk
+ - sprd,sc9863a-pmu-gate
+ - sprd,sc9863a-pll
+ - sprd,sc9863a-mpll
+ - sprd,sc9863a-rpll
+ - sprd,sc9863a-dpll
+ - sprd,sc9863a-aon-clk
+ - sprd,sc9863a-apahb-gate
+ - sprd,sc9863a-aonapb-gate
+ - sprd,sc9863a-mm-gate
+ - sprd,sc9863a-mm-clk
+ - sprd,sc9863a-vspahb-gate
+ - sprd,sc9863a-apapb-gate
+
+ clocks:
+ description: |
+ The input parent clock(s) phandle for this clock, only list fixed
+ clocks which are decleared in devicetree.
+
+ clock-names:
+ description: |
+ Clock name strings used for driver to reference.
+
+ reg:
+ description: |
+ Contain the registers base address and length. It must be configured
+ only if no 'sprd,syscon' under the node.
+
+ sprd,syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ The phandle to the syscon which is in the same address area with
+ the clock, and so we can get regmap for the clocks from the
+ syscon device.
+
+required:
+ - compatible
+ - '#clock-cells'
+
+examples:
+ - |
+ ap_clk: clock-controller@21500000 {
+ compatible = "sprd,sc9863a-ap-clk";
+ reg = <0 0x21500000 0 0x1000>;
+ clocks = <&ext_32k>, <&ext_26m>;
+ clock-names = "ext-32k", "ext-26m";
+ #clock-cells = <1>;
+ };
+
+ - |
+ apahb_gate: apahb-gate {
+ compatible = "sprd,sc9863a-apahb-gate";
+ sprd,syscon = <&ap_ahb_regs>;
+ #clock-cells = <1>;
+ };
+
+...
--
2.20.1
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