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Subject[PATCH 3.16 096/136] perf/x86/amd/ibs: Handle erratum #420 only on the affected CPU family (10h)
3.16.80-rc1 review patch.  If anyone has any objections, please let me know.


From: Kim Phillips <>

commit e431e79b60603079d269e0c2a5177943b95fa4b6 upstream.

This saves us writing the IBS control MSR twice when disabling the

I searched revision guides for all families since 10h, and did not
find occurrence of erratum #420, nor anything remotely similar:
so we isolate the secondary MSR write to family 10h only.

Also unconditionally update the count mask for IBS Op implementations
that have read & writeable current count (CurCnt) fields in addition
to the MaxCnt field. These bits were reserved on prior
implementations, and therefore shouldn't have negative impact.

Signed-off-by: Kim Phillips <>
Signed-off-by: Peter Zijlstra (Intel) <>
Cc: Alexander Shishkin <>
Cc: Arnaldo Carvalho de Melo <>
Cc: Arnaldo Carvalho de Melo <>
Cc: Borislav Petkov <>
Cc: H. Peter Anvin <>
Cc: Jiri Olsa <>
Cc: Linus Torvalds <>
Cc: Mark Rutland <>
Cc: Namhyung Kim <>
Cc: Stephane Eranian <>
Cc: Thomas Gleixner <>
Cc: Vince Weaver <>
Fixes: c9574fe0bdb9 ("perf/x86-ibs: Implement workaround for IBS erratum #420")
Signed-off-by: Ingo Molnar <>
[bwh: Backported to 3.16:
- Don't update the count mask; we don't use or define the CurCnt fields here
- Adjust filename]
Signed-off-by: Ben Hutchings <>
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -351,7 +351,8 @@ static inline void perf_ibs_disable_even
struct hw_perf_event *hwc, u64 config)
config &= ~perf_ibs->cnt_mask;
- wrmsrl(hwc->config_base, config);
+ if (boot_cpu_data.x86 == 0x10)
+ wrmsrl(hwc->config_base, config);
config &= ~perf_ibs->enable_mask;
wrmsrl(hwc->config_base, config);
 \ /
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