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SubjectRe: [PATCH v3 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
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Quoting Sandeep Maheswaram (2019-12-15 21:39:01)
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> new file mode 100644
> index 0000000..c8eda58
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -0,0 +1,153 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SuperSpeed DWC3 USB SoC controller
> +
> +maintainers:
> + - Manu Gautam <mgautam@codeaurora.org>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - qcom,msm8996-dwc3
> + - qcom,msm8998-dwc3
> + - qcom,sdm845-dwc3
> + - const: qcom,dwc3
> +
> + reg:
> + description: Offset and length of register set for QSCRATCH wrapper
> + maxItems: 1
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]

Hm... ok. Interesting.

> +
> + power-domains:
> + description: specifies a phandle to PM domain provider node
> + maxItems: 1
> +
> + clocks:
> + description:
> + A list of phandle and clock-specifier pairs for the clocks
> + listed in clock-names.
> + minItems: 3
> + items:
> + - description: System Config NOC clock. Not present on "qcom,msm8996-dwc3" compatible.
> + - description: Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation
> + - description: System bus AXI clock. Not present on "qcom,msm8996-dwc3" compatible.
> + - description: Mock utmi clock needed for ITP/SOF generation in host mode.Its frequency should be 19.2MHz.
> + - description: Sleep clock, used for wakeup when USB3 core goes into low power mode (U3).
> +
> + clock-names:
> + minItems: 3
> + items:
> + - const: cfg_noc
> + - const: core
> + - const: iface
> + - const: mock_utmi
> + - const: sleep

Order matters. Can 'core' and 'iface' come first and then the others
after that? Same comment applies to clocks property.

> +
> + assigned-clocks:
> + items:
> + - description: Phandle to MOCK_UTMI_CLK.
> + - description: Phandle to MASTER_CLK.
> +
> + assigned-clock-rates:
> + description:
> + Should be 19.2MHz (19200000) for MOCK_UTMI_CLK
> + >=125MHz (125000000) for MASTER_CLK in SS mode
> + >=60MHz (60000000) for MASTER_CLK in HS mode
> + maxItems: 2
> +
> + resets:
> + maxItems: 1
> +
> + interrupts:
> + description:
> + Specifies interrupts from controller wrapper used
> + to wakeup from low power/suspend state. Must contain
> + one or more entry for interrupt-names property.
> + items:
> + - description: The interrupt that is asserted when a wakeup event is received on USB2 bus.
> + - description: The interrupt that is asserted when a wakeup event is received on USB3 bus.
> + - description: Wakeup event on DM line.
> + - description: Wakeup event on DP line.
> +
> + interrupt-names:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + items:
> + - const: hs_phy_irq
> + - const: ss_phy_irq
> + - const: dm_hs_phy_irq
> + - const: dp_hs_phy_irq
> +
> + qcom,select-utmi-as-pipe-clk:
> + description:

Don't these multi-line descriptions need a pipe, | ?

> + If present, disable USB3 pipe_clk requirement.
> + Used when dwc3 operates without SSPHY and only
> + HS/FS/LS modes are supported.
> + type: boolean
> +
> +# Required child node:
> +
> +patternProperties:
> + "^dwc3@[0-9a-f]+$":
> + type: object
> + description:
> + A child node must exist to represent the core DWC3 IP block
> + The content of the node is defined in dwc3.txt.
> +
> +# Phy documentation is provided in the following places:
> +# Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY
> +# Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - power-domains
> + - clocks
> + - clock-names

Are 'interrupts' required?

> +
> +examples:
> + - |
> + usb3_0: usb30@a6f8800 {

Should node name be something like 'usb3'? Or is this usb 3.0 so it's
'usb30'?

> + compatible = "qcom,dwc3";
> + reg = <0xa6f8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
> + "dm_hs_phy_irq", "dp_hs_phy_irq";

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