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Subject[PATCH 1/3] clocksource: davinci: work around a clocksource problem on dm365 SoC
Date
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>

The DM365 platform has a strange quirk (only present when using ancient
u-boot - mainline u-boot v2013.01 and later works fine) where if we
enable the second half of the timer in periodic mode before we do its
initialization - the time won't start flowing and we can't boot.

When using more recent u-boot, we can enable the timer, then reinitialize
it and all works fine.

I've been unable to figure out why that is, but a workaround for this
is straightforward - just cache the enable bits for tim34.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/clocksource/timer-davinci.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c
index 62745c962049..1c22443acaeb 100644
--- a/drivers/clocksource/timer-davinci.c
+++ b/drivers/clocksource/timer-davinci.c
@@ -64,6 +64,8 @@ static struct {
unsigned int tim_off;
} davinci_clocksource;

+static unsigned int davinci_clocksource_tim32_mode;
+
static struct davinci_clockevent *
to_davinci_clockevent(struct clock_event_device *clockevent)
{
@@ -94,7 +96,7 @@ static void davinci_tim12_shutdown(void __iomem *base)
* halves. In this case TIM34 runs in periodic mode and we must
* not modify it.
*/
- tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
+ tcr |= davinci_clocksource_tim32_mode <<
DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;

writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
@@ -107,7 +109,7 @@ static void davinci_tim12_set_oneshot(void __iomem *base)
tcr = DAVINCI_TIMER_ENAMODE_ONESHOT <<
DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
/* Same as above. */
- tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
+ tcr |= davinci_clocksource_tim32_mode <<
DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;

writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
@@ -206,6 +208,8 @@ static void davinci_clocksource_init_tim34(void __iomem *base)
writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
+
+ davinci_clocksource_tim32_mode = DAVINCI_TIMER_ENAMODE_PERIODIC;
}

/*
--
2.23.0
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