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SubjectRe: [PATCH v2, 2/2] drm/mediatek: Add ctm property support
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Hi, Yongqiang:

On Fri, 2019-12-13 at 16:11 +0800, Yongqiang Niu wrote:
> On Fri, 2019-12-13 at 15:57 +0800, CK Hu wrote:
> > On Fri, 2019-12-13 at 15:28 +0800, Yongqiang Niu wrote:
> > > Add ctm property support
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 ++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 ++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++
> > > 3 files changed, 78 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > index 9a8e1d4..db3031e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > > @@ -614,8 +614,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> > > if (mtk_crtc->event)
> > > mtk_crtc->pending_needs_vblank = true;
> > > if (crtc->state->color_mgmt_changed)
> > > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> > > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> > > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
> > > + }
> > > mtk_drm_crtc_hw_config(mtk_crtc);
> > > }
> > >
> > > @@ -734,6 +736,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > > int pipe = priv->num_pipes;
> > > int ret;
> > > int i;
> > > + bool has_ctm = false;
> > > uint gamma_lut_size = 0;
> > >
> > > if (!path)
> > > @@ -787,6 +790,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > mtk_crtc->ddp_comp[i] = comp;
> > >
> > > + if (comp->funcs->ctm_set)
> > > + has_ctm = true;
> > > +
> > > if (comp->funcs->gamma_set)
> > > gamma_lut_size = MTK_LUT_SIZE;
> > > }
> > > @@ -812,7 +818,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > >
> > > if (gamma_lut_size)
> > > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
> > > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
> > > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
> >
> > May enable color management when has gamma or ctm.
> >
> > Regards,
> > CK
> >
> drm_crtc_enable_color_mgmt will check the parameter validation.
> if has_ctm is false, will not attach ctm property.
> if gamma_lut_size is zero, will not attach gamma property.

You're right. So

Reviewed-by: CK Hu <ck.hu@mediatek.com>

>
>
> > > priv->num_pipes++;
> > > mutex_init(&mtk_crtc->hw_lock);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index cb3296f..182990a 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -37,7 +37,15 @@
> > > #define CCORR_EN BIT(0)
> > > #define DISP_CCORR_CFG 0x0020
> > > #define CCORR_RELAY_MODE BIT(0)
> > > +#define CCORR_ENGINE_EN BIT(1)
> > > +#define CCORR_GAMMA_OFF BIT(2)
> > > +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> > > #define DISP_CCORR_SIZE 0x0030
> > > +#define DISP_CCORR_COEF_0 0x0080
> > > +#define DISP_CCORR_COEF_1 0x0084
> > > +#define DISP_CCORR_COEF_2 0x0088
> > > +#define DISP_CCORR_COEF_3 0x008C
> > > +#define DISP_CCORR_COEF_4 0x0090
> > >
> > > #define DISP_DITHER_EN 0x0000
> > > #define DITHER_EN BIT(0)
> > > @@ -188,7 +196,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > {
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> > > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> > > }
> > >
> > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> > > @@ -201,6 +209,57 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> > > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> > > }
> > >
> > > +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> > > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> > > +{
> > > + u16 r;
> > > +
> > > + /* Sign bit. */
> > > + r = in & BIT_ULL(63) ? BIT(11) : 0;
> > > +
> > > + if ((in & GENMASK_ULL(62, 33)) > 0) {
> > > + /* identity value 0x100000000 -> 0x400, */
> > > + /* if bigger this, set it to max 0x7ff. */
> > > + r |= GENMASK(10, 0);
> > > + } else {
> > > + /* take the 11 most important bits. */
> > > + r |= (in >> 22) & GENMASK(10, 0);
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + struct drm_property_blob *blob = state->ctm;
> > > + struct drm_color_ctm *ctm;
> > > + const u64 *input;
> > > + uint16_t coeffs[9] = { 0 };
> > > + int i;
> > > + struct cmdq_pkt *cmdq_pkt = NULL;
> > > +
> > > + if (!blob)
> > > + return;
> > > +
> > > + ctm = (struct drm_color_ctm *)blob->data;
> > > + input = ctm->matrix;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> > > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> > > +
> > > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> > > + comp, DISP_CCORR_COEF_0);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> > > + comp, DISP_CCORR_COEF_1);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> > > + comp, DISP_CCORR_COEF_2);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> > > + comp, DISP_CCORR_COEF_3);
> > > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> > > + comp, DISP_CCORR_COEF_4);
> > > +}
> > > +
> > > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > > @@ -271,6 +330,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> > > .config = mtk_ccorr_config,
> > > .start = mtk_ccorr_start,
> > > .stop = mtk_ccorr_stop,
> > > + .ctm_set = mtk_ccorr_ctm_set,
> > > };
> > >
> > > static const struct mtk_ddp_comp_funcs ddp_dither = {
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > index 384abae..20fe55d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > > @@ -92,6 +92,8 @@ struct mtk_ddp_comp_funcs {
> > > struct drm_crtc_state *state);
> > > void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> > > void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> > > + void (*ctm_set)(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state);
> > > };
> > >
> > > struct mtk_ddp_comp {
> > > @@ -205,6 +207,13 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> > > comp->funcs->bgclr_in_off(comp);
> > > }
> > >
> > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + if (comp->funcs && comp->funcs->ctm_set)
> > > + comp->funcs->ctm_set(comp, state);
> > > +}
> > > +
> > > int mtk_ddp_comp_get_id(struct device_node *node,
> > > enum mtk_ddp_comp_type comp_type);
> > > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> >
> >
>
>

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