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SubjectRe: RISC-V nommu support v6
Paul Walmsley <paul.walmsley@sifive.com> 於 2019年11月23日 週六 上午10:24寫道:
>
> On Thu, 31 Oct 2019, Christoph Hellwig wrote:
>
> > On Wed, Oct 30, 2019 at 01:21:21PM -0700, Paul Walmsley wrote:
> > > I tried building this series from your git branch mentioned above, and
> > > booted it with a buildroot userspace built from your custom buildroot
> > > tree. Am seeing some segmentation faults from userspace (below).
> > >
> > > Am still planning to merge your patches.
> > >
> > > But I'm wondering whether you are seeing these segmentation faults also?
> > > Or is it something that might be specific to my test setup?
> >
> > I just built a fresh image using make -j4 with that report and it works
> > perfectly fine with my tree.
>
> Another colleague just gave this a quick test, following your instructions
> as I did. He encountered the same segmentation faulting issue. Might be
> worth taking a look at this once v5.5-rc1 is released. Could be a
> userspace issue, though.

Hi Christoph,

I think it should be replaced with this macro for cores without S-mode.

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 9bca97ffb67a..5c8b24bf4e4e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -248,7 +248,7 @@ ENTRY(reset_regs)
li t4, 0
li t5, 0
li t6, 0
- csrw sscratch, 0
+ csrw CSR_SCRATCH, 0

#ifdef CONFIG_FPU
csrr t0, CSR_MISA
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