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SubjectRe: [PATCH 3.16 31/72] KVM: x86: Manually calculate reserved bits when loading PDPTRS
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On Mon, 2019-12-09 at 07:49 -0800, Sean Christopherson wrote:
> On Sun, Dec 08, 2019 at 01:53:15PM +0000, Ben Hutchings wrote:
> > 3.16.79-rc1 review patch. If anyone has any objections, please let me know.
> >
> > ------------------
> >
> > From: Sean Christopherson <sean.j.christopherson@intel.com>
> >
> > commit 16cfacc8085782dab8e365979356ce1ca87fd6cc upstream.
>
> You'll also want to pull in two PAE related fixes (in this order):
>
> d35b34a9a70e ("kvm: mmu: Don't read PDPTEs when paging is not enabled")

I've added this, thanks.

> bf03d4f93347 ("KVM: x86: introduce is_pae_paging")
>
> The "introduce is_pae_paging" has an undocumented bug fix. IIRC it
> manifests as an unexpected #GP on MOV CR3 in 64-bit mode. Here's the blurb
> I added to the backports for 4.x.
>
> Moving to the common helper also fixes a subtle bug in kvm_set_cr3()
> where it fails to check is_long_mode() and results in KVM incorrectly
> attempting to load PDPTRs for a 64-bit guest.

The 3.16, 4.4, and 4.9 branches have slightly different conditions in
kvm_set_cr3():

if (is_long_mode(vcpu)) {
if (cr3 & CR3_L_MODE_RESERVED_BITS)
return 1;
} else if (is_pae(vcpu) && is_paging(vcpu) &&
!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
return 1;

So load_pdptrs() already won't be called if is_long_mode() returns
true, and this fix shouldn't be needed.

Ben.

--
Ben Hutchings
Experience is directly proportional to the value of equipment destroyed
- Carolyn Scheppner


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