Messages in this thread |  | | From | Yash Shah <> | Subject | RE: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs | Date | Mon, 18 Nov 2019 07:50:48 +0000 |
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> -----Original Message----- > From: Marc Zyngier <maz@kernel.org> > Sent: 12 November 2019 18:28 > To: Yash Shah <yash.shah@sifive.com> > Cc: linus.walleij@linaro.org; bgolaszewski@baylibre.com; > robh+dt@kernel.org; mark.rutland@arm.com; palmer@dabbelt.com; Paul > Walmsley ( Sifive) <paul.walmsley@sifive.com>; aou@eecs.berkeley.edu; > tglx@linutronix.de; jason@lakedaemon.net; bmeng.cn@gmail.com; > atish.patra@wdc.com; Sagar Kadam <sagar.kadam@sifive.com>; linux- > gpio@vger.kernel.org; devicetree@vger.kernel.org; linux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Sachin Ghadi > <sachin.ghadi@sifive.com> > Subject: Re: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs > > On 2019-11-12 13:21, Yash Shah wrote: > > Adds the GPIO driver for SiFive RISC-V SoCs. > > > > Signed-off-by: Wesley W. Terpstra <wesley@sifive.com> > > [Atish: Various fixes and code cleanup] > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > [...] > > > +static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > > + unsigned int child, > > + unsigned int child_type, > > + unsigned int *parent, > > + unsigned int *parent_type) > > +{ > > + /* All these interrupts are level high in the CPU */ > > + *parent_type = IRQ_TYPE_LEVEL_HIGH; > > It is bizare that you enforce LEVEL_HIGH here, while setting it to NONE in the > PLIC driver. These things should be consistent.
Will change this to IRQ_TYPE_NONE.
> > > + *parent = child + 7; > > Irk, magic numbers...
This is the offset for GPIO IRQs. Will add a macro for this. Thanks for your comments!
- Yash
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