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SubjectRe: [GIT PULL] RISC-V updates for v5.4-rc2
On Fri, Oct 4, 2019 at 10:36 AM Paul Walmsley <> wrote:
> - Ensure that exclusive-load reservations are terminated after system
> call or exception handling. This primarily affects QEMU, which does
> not expire load reservations.

Grr. Can somebody talk sense to the RISC-V architects?

Copying the PowerPC model was broken. PowerPC has now become the
absolute worst architecture out there wrt just about any memory
ordering issues, and the exclusive reservation is just another example
of that.

ARMv8 and even alpha got this right, and clear the reservation on
return from traps/exceptions.

Why did RISC-V copy the power model? (Yeah, I realize that ARM did too
originally, but they learnt from their mistakes).

Oh well.


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