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SubjectRe: [PATCH v3 2/5] clk: rockchip: fix up the frac clk get rate error
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Quoting Elaine Zhang (2019-09-26 20:00:41)
> support fractional divider with only one level parent clock

Please put a lot more description in here. A single sentence doesn't
help anyone understand the motivation for the change.

>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index fac5a4a3f5c3..8f77c3f9fab7 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
> if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
> (fd->max_prate && fd->max_prate < p_rate)) {
> p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
> - p_parent_rate = clk_hw_get_rate(p_parent);
> - *parent_rate = p_parent_rate;
> - if (fd->max_prate && p_parent_rate > fd->max_prate) {
> - div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
> - *parent_rate = p_parent_rate / div;
> + if (!p_parent) {
> + *parent_rate = p_rate;
> + } else {
> + p_parent_rate = clk_hw_get_rate(p_parent);
> + *parent_rate = p_parent_rate;
> + if (fd->max_prate && p_parent_rate > fd->max_prate) {
> + div = DIV_ROUND_UP(p_parent_rate,
> + fd->max_prate);
> + *parent_rate = p_parent_rate / div;
> + }
> }
>
> if (*parent_rate < rate * 20) {
> - pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
> - clk_hw_get_name(hw), *parent_rate, rate);
> + pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
> + clk_hw_get_name(hw), *parent_rate, rate);

Hm.. now it's changed to a warning?

> *m = 0;
> *n = 1;
> return;
> --
> 1.9.1
>
>
>

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