[lkml]   [2019]   [Oct]   [25]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
On 2019-10-25 04:03, Rob Herring wrote:
> On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
> <> wrote:
>> Hi Rob,
>> On 2019-10-24 01:19, Rob Herring wrote:
>> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
>> > <> wrote:
>> >>
>> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
>> >>
>> >> > LLCC behaviour is controlled by the configuration data set
>> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
>> >> > Also convert the existing bindings to json-schema and add
>> >> > the compatible for SC7180 SoC.
>> >> >
>> >>
>> >> Thanks for the patches and thanks for the review Stephen. Series
>> >> applied
>> >
>> > And they break dt_binding_check. Please fix.
>> >
>> I did check this and think that the error log from dt_binding_check is
>> not valid because it says cache-level is a required property [1], but
>> there is no such property in LLCC bindings.
> Then you should point out the issue and not just submit stuff ignoring
> it. It has to be resolved one way or another.

I did not ignore it. When I ran the dt-binding check locally, it did not
error out and just passed on [1] and it was my bad that I did not check
the entire build logs to see if llcc dt binding check had some warning
not. But this is the usual case where most of us don't look at the
build logs to check if there is a warning or not. We notice if there is
immediate exit/fail in case of some warning/error. So it would be good
we fail the dt-binding check build if there is some warning/error or
provide some option to strict build to fail on warning, maybe there is
a flag to do this?

After submitting the patch, I noticed this build failure on and was waiting for your reply.


> If you refer to the DT spec[1], cache-level is required. The schema is
> just enforcing that now. It's keying off the node name of
> 'cache-controller'.

This is not L2 or L3 cache, this is a system cache (last level cache)
shared by
clients other than just CPU. So I don't know how do we specify
cache-level for
this, let me know if you have some pointers.


QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
of Code Aurora Forum, hosted by The Linux Foundation

 \ /
  Last update: 2019-10-25 09:56    [W:0.136 / U:0.208 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site